In the verification process of an integrated circuit (IC) there often arises a need to verify functionality of a portion of the circuit from one Flip-Flop (FF) to another along a data path. It is useful to have an efficient and reliable method for these verification tests, as they usually involve a large number of logic components, which complicate the verification testing.
In order to solve issues related to verification of complex designs various ways of abstraction are used. For example, a memory block is not described by its components but by an abstraction of a memory, once the memory block has been tested and verified for correctness of the design. Other blocks include processors, clocks, power regulators, multiplexers, and so on and so forth. However, in many cases circuits are designed that are complex and not built using standard intellectual property (IP) blocks. For example, a protocol may have multiple state machines that control various aspects of a specific IC, however, it cannot be readily abstracted to pin-point the specific state machine relevant for a given property using prior art techniques.
It would therefore be advantageous to provide a method that overcomes the limitations of the prior art. Specifically, it would be advantageous to provide an automatic solution for abstracting portions of circuits of an IC that are not provided explicitly as integral blocks.